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Magazine Name : Ieee Transactions On Very Large Scale Intergration (Vlsi) Systems
Year : 2002Volume number : 10Issue:06
Special Issue On On-Chip Inductance In High-Speed Integrated Circuits(Article) Subject:
High-Speed
Author:
Y. I
Ismail
S
Krauter
page:
683
-
684
On-Chip Inductance Cons And Pros(Article) Subject:
Inductance Measurement
Author:
Y. I
Ismail
page:
685
-
694
A Comprehensive 2-D Inductance Modeling Approach For Vsli Interconnects: Frequency -Dependent Extraction And Campact Circuit Model Synthesis(Article) Subject:
Model Synthesis
Author:
G.V.
Kopcsay
B.
Krauter
page:
695
-
711
On-Chip Induction Modeling : Basics And Advanced Methods(Article) Subject:
Advanced Method
Author:
M. F
Beatty
L. T
Pileggi
page:
712
-
729
Induction Model And Analysis Methodology For High -Speed On-Chip Interconnects(Article) Subject:
Inductance Model
Author:
K
Gala
page:
730
-
745
Efficient Inductance Extraction Using Circuit-Aware Techniques(Article) Subject:
Extraction Algorithms
Author:
H
Hu
S.S
Sapantnekar
page:
746
-
761
Inductive Properties Of High Performance Power Distribution Grids(Article) Subject:
High Performance
Author:
A.V.
Mezhiba
E. G
Friedman
page:
762
-
776
Electrical Interconnects Revitalized(Article) Subject:
Interconnect
Author:
C.
Svensson
page:
777
-
788
Managing On-Chip Inductive Effects(Article) Subject:
Inductive Components
,
Effects Of Bearing
Author:
Yehia
Massoud
S.
Majors
page:
789
-
798
Effective On-Chip Inductance Modeling For Multiple Signal Lines And Application To Repeater Insertaion(Article) Subject:
Modeling
Author:
Y
Cao
N.H.
Chang
page:
799
-
805
Analysis And Comparision On Full Adder Block In Submicron Technology(Article) Subject:
Technological Acquiescence
Author:
M
Alioto
G
Palumbo
page:
806
-
823
Net-Based Force-Directed Macrocell Placement For Wirelength Optimization(Article) Subject:
Optimization
Author:
S.
Alupoaei
Srinivas
Katkoori
page:
824
-
835
Probability-Based Approach To Rectilinear Steiner Tree Problems(Article) Subject:
Probabilistic
Author:
C.
Chen
J.
Zhao
page:
836
-
843
A Clock Power Model To Evaluate Impact Of Architectural And Technology Optimization(Article) Subject:
Architechtural Style
Author:
D.E.
Duarte
N.
Vijaykrishnan
page:
844
-
855
Induction -Base System-Level Power Evaluation Of System-On-A-Chip Peripheral Cores(Article) Subject:
Peripheral End
Author:
T. D
Givargis
F
Vahid
page:
856
-
863
Algorithm Level Comparing Using Implementation Diversity : A Register Level Concurrent Error Detection Technique(Article) Subject:
Level Crossing Problems
Author:
R.
Karri
K.
Wu
page:
864
-
875
Leakage Power Analysis And Reduction During Behavioral Synthesis(Article) Subject:
Synthesis
Author:
K.S.
Khouri
N. K
Jha
page:
876
-
885
Aritararily Shaped Rectilinear Module Placement Using The Transitive Closure Graph Representation(Article) Subject:
Rectilinear Model
Author:
J.M.
Lin
H.L
Chen
page:
886
-
901
Area-Efficient High -Speed Decoding Schemes Turbo Decoders(Article) Subject:
Decoding
Author:
Z
Wang
page:
902
-
912
A Comparative Analysis Of Low-Power Low-Voltage Dual-Edge-Triggered Flip-Flops(Article) Subject:
Analysis
,
Low-Power
Author:
W
Chung
T
Lo
page:
913
-
918
Design Of A Dynamic Pipelined Architecture For Fuzzy Color Correction(Article) Subject:
Color Correction
Author:
J.M
Jou
S. R
Kuang
page:
924
-
928
Theoretical Analysis Of Bus-Invert Coding(Article) Subject:
Coding
Author:
R.-B
Lin
C
Tsai
page:
929
-
934
A Methodology For System Level Suynthesis Of Mixed Signsl Application(Article) Subject:
Methodological Adaptations
Author:
P.
Oehler
K. A
Grimmelsman
page:
935
-
941
Functional Vector Generation Foe Sequential Hdl Models Under An Obervability -Based Code Coverage Metric(Article) Subject:
Generation Function
Author:
F
Fallah
Syed
Ashar Navaid
page:
9419
-
923
Enpco: An Entropy -Based Partition -Codec Algorithm To Reduce Power For Bipartition-Codec Architecture In Pipelined(Article) Subject:
Power
Author:
Y
Ruan
page:
942
-
949